1. Field of the Invention
The present invention generally relates to a thin film magnetic memory device. More particularly, the present invention relates to a random access memory (RAM) including memory cells having a magnetic tunnel junction (MTJ).
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device is a memory device capable of non-volatile data storage using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit and also capable of random access to each thin film magnetic element as a memory cell.
In particular, recent announcement shows that the use of thin film magnetic elements having a magnetic tunnel junction (MTJ) as memory cells significantly improves performance of the MRAM device. The MRAM device including memory cells having a magnetic tunnel junction is disclosed in technical documents such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, February 2000, and xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, February 2000.
FIG. 16 schematically shows the structure of a memory cell having a magnetic tunnel junction (hereinafter, sometimes simply referred to as xe2x80x9cMTJ memory cellxe2x80x9d).
Referring to FIG. 16, the MTJ memory cell includes a tunneling magneto-resistance element TMR having an electric resistance varying according to a magnetically written storage data level, and an access element ATR. Access transistor ATR is connected in series with tunneling magneto-resistance element TMR between a bit line BL and a source line SRL. A field effect transistor formed on a semiconductor substrate is typically used as access transistor ATR.
A bit line BL, a write digit line WDL, a word line WL and a source line SRL are provided for the MTJ memory cell. Bit line BL and write digit line WDL pass data write currents of different directions therethrough in data write operation, respectively. Word line WL is used to conduct data read operation. Source line SRL pulls tunneling magneto-resistance element TMR down to a ground voltage GND in data read operation. In data read operation, tunneling magneto-resistance element TMR is electrically coupled between source line SRL (ground voltage GND) and bit line BL in response to turning-ON of access transistor ATR.
FIG. 17 is a conceptual diagram illustrating data write operation to the MTJ memory cell.
Referring to FIG. 17, tunneling magneto-resistance element TMR has a ferromagnetic material layer FL having a fixed magnetization direction (hereinafter, sometimes simply referred to as xe2x80x9cfixed magnetic layerxe2x80x9d), and a ferromagnetic material layer VL that is magnetized in the direction according to an external magnetic field (hereinafter, sometimes simply referred to as xe2x80x9cfree magnetic layerxe2x80x9d). A tunneling barrier (tunneling film) TB of an insulator film is interposed between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized either in the same (parallel) direction as, or in the opposite direction to, that of fixed magnetic layer FL according to the write data level. Fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL form a magnetic tunnel junction.
The electric resistance of tunneling magneto-resistance element TMR varies according to the relation between the respective magnetization directions of fixed magnetic layer FL and free magnetic layer VL. More specifically, the electric resistance of tunneling magneto-resistance element TMR is minimized (Rmin) when fixed magnetic layer FL and free magnetic layer VL have parallel magnetization directions, and is maximized (Rmax) when they have opposite (antiparallel) magnetization directions.
In data write operation, word line WL is inactivated and access transistor ATR is turned OFF. In this state, a data write current for magnetizing free magnetic layer VL is applied to each of bit line BL and write digit line WDL in the direction according to the write data level.
FIG. 18 is a conceptual diagram illustrating the relation between the data write current and the magnetization direction of the tunneling magneto-resistance element in data write operation.
Referring to FIG. 18, the abscissa H(EA) indicates a magnetic field that is applied to free magnetic layer VL of tunneling magneto-resistance element TMR in the easy-axis (EA) direction. The ordinate H(HA) indicates a magnetic field that is applied to free magnetic layer VL in the hard-axis (HA) direction. Magnetic fields H(EA), H(HA) respectively correspond to two magnetic fields produced by the currents flowing through bit line BL and write digit line WDL.
In the MTJ memory cell, fixed magnetic layer FL is magnetized in the fixed direction along the easy axis of free magnetic layer VL. Free magnetic layer VL is magnetized either in the direction parallel or antiparallel (opposite) to that of fixed magnetic layer FL along the easy axis according to the storage data level (xe2x80x9c1xe2x80x9dand xe2x80x9c0xe2x80x9d). The MTJ memory cell is thus capable of storing 1-bit data (xe2x80x9c1xe2x80x9dand xe2x80x9c0xe2x80x9d) according to the two magnetization directions of free magnetic layer VL.
The magnetization direction of free magnetic layer VL can be rewritten only when the sum of the applied magnetic fields H(EA) and H(HA) reaches the region outside the asteroid characteristic line shown in the FIG. 18. In other words, the magnetization direction of free magnetic layer VL will not switch if an applied data write magnetic field corresponds to the region inside the asteroid characteristic line.
As shown by the asteroid characteristic line, applying a magnetic field of the hard-axis direction to free magnetic layer VL enables reduction in a magnetization threshold value required to change the magnetization direction along the easy axis.
When the operation point of the data write operation is designed as in the example of FIG. 18, a data write magnetic field of the easy-axis direction is designed to have strength HWR in the MTJ memory cell to be written. In other words, the data write current to be applied to bit line BL or write digit line WDL is designed to produce such a data write magnetic field HWR. In general, data write magnetic field HWR is defined by the sum of a switching magnetic field HSW required to switch the magnetization direction and a margin xcex94H. Data write magnetic field HWR is thus defined by HWR=HSW+xcex94H.
In order to rewrite the storage data of the MTJ memory cell, that is, the magnetization direction of tunneling magneto-resistance element TMR, a data write current of at least a prescribed level must be applied to both write digit line WDL and bit line BL. Free magnetic layer VL in tunneling magneto-resistance element TMR is thus magnetized in the direction parallel or opposite (antiparallel) to that of fixed magnetic layer FL according to the direction of the data write magnetic field along the easy axis (EA). The magnetization direction written to tunneling magneto-resistance element TMR, i.e., the storage data of the MTJ memory cell, is held in a non-volatile manner until another data write operation is conducted.
FIG. 19 is a conceptual diagram illustrating data read operation from the MTJ memory cell.
Referring to FIG. 19, in data read operation, access transistor ATR is turned ON in response to activation of word line WL. As a result, tunneling magneto-resistance element TMR pulled down to ground voltage GND is electrically coupled to bit line BL.
If bit line BL is then pulled up to a prescribed voltage, a memory cell current Icell according to the electric resistance of tunneling magneto-resistance element TMR, that is, the storage data level of the MTJ memory cell, flows through a current path including bit line BL and tunneling magneto-resistance element TMR. For example, the storage data can be read from the MTJ memory cell based on comparison between memory cell current Icell and a prescribed reference current.
The electric resistance of tunneling magneto-resistance element TMR thus varies according to the magnetization direction that is rewritable by an applied data write magnetic field. Accordingly, non-volatile data storage can be realized by using electric resistances Rmax and Rmin of tunneling magneto-resistance element TMR as the respective storage data levels (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d).
FIG. 20 shows the structure of the MTJ memory cell formed on a semiconductor substrate.
Referring to FIG. 20, access transistor ATR formed on a semiconductor main substrate SUB has source/drain regions (n-type regions) 510, 520 and a gate 530. Source/drain region 510 is electrically coupled to source line SRL through a metal film formed in a contact hole 541.
Write digit line WDL is formed in a metal wiring layer above source line SRL. Tunneling magneto-resistance element TMR is formed in a layer above write digit line WDL. Tunneling magneto-resistance element TMR is electrically coupled to source/drain region 520 of access transistor ATR through a strap SL and a metal film formed in a contact hole 540. Strap SL is formed from an electrically conductive material, and electrically couples tunneling magneto-resistance element TMR to access transistor ATR.
Bit line BL is electrically coupled to tunneling magneto-resistance element TMR, and is formed in a layer on tunneling magneto-resistance element TMR. As described before, in data write operation, a data write current must be supplied to both bit line BL and write digit line WDL. In data read operation, however, access transistor ATR is turned ON in response to activation of word line WL to, e.g., a high voltage state. As a result, tunneling magneto-resistance element TMR pulled down to ground voltage GND through access transistor ATR is electrically coupled to bit line BL.
In data write operation of the MRAM device, a data write current must be supplied to both write digit line WDL and bit line BL corresponding to the selected memory cell. These data write currents are required to generate a data write magnetic field having at least a prescribed strength in tunneling magneto-resistance element TMR of the selected memory cell. Therefore, an applied data write current must be generally on the order of several milliamperes (mA).
Meanwhile, increased data processing capacity and data processing speed are required in applications of the semiconductor memory device. In other words, a so-called multi-bit semiconductor memory device is required which is capable of receiving and outputting data of a plurality of bits in parallel in each data read operation and data write operation.
Using the above MRAM device as such a multi-bit semiconductor memory device would significantly increase current consumption in data write operation.
Moreover, a magnetic field having the direction according to a write data level must be generated for the selected memory cell along the easy axis (EA) of tunneling magneto-resistance element TMR. In other words, write drivers for controlling the direction of the data write current according to the write data level must be provided for either bit lines BL or write digit lines WDL. Such a write driver must be provided in each memory cell column or each memory cell row. When the write drivers have a complex structure, it is difficult to reduce the area of the MRAM device.
It is an object of the present invention to provide an MRAM device having a multi-bit structure with low current consumption.
It is another object of the present invention to provide an MRAM device including write drivers with simple structures.
In summary, according to one aspect of the present invention, a thin film magnetic memory device for writing K-bit write data in parallel (where K is an integer of at least 2) includes a plurality of memory cells, a plurality of write digit lines, a plurality of bit lines, at least K current return lines and a write driver. The plurality of memory cells are arranged in a matrix. Each memory cell has an electric resistance according to storage data magnetically written therein. The plurality of write digit lines are arranged respectively corresponding to the memory cell rows, for passing therethrough a prescribed write current of a fixed direction in a selected row in data write operation. The plurality of bit lines are arranged respectively corresponding to the memory cell columns, for passing therethrough a data write current of a direction according to a level of the write data. The plurality of current return lines are arranged respectively corresponding to the memory cell columns. Each current return line turns back the data write current flowing through one of K selected bit lines of K columns selected to write the K-bit write data as necessary. The write driver supplies the data write current to the K selected bit lines in directions respectively corresponding to the K-bit write data. The write driver connects the K selected bit lines and L of the current return lines in series between first and second voltages in the data write operation (where L is an integer in a range of 0 to K).
In the above thin film magnetic memory device, a bit line write current can be supplied to the selected bit lines in the directions respectively corresponding to a plurality of bits of write data. This enables the data of the plurality of bits to be written in parallel without increasing current consumption.
According to another aspect of the present invention, a thin film magnetic memory device includes a memory array, a plurality of write digit lines, first and second write current control lines, a first connection control portion, a second connection control portion, a plurality of column selection lines, and write drivers. The memory array has a plurality of memory cells arranged in a matrix. Each memory cell has an electric resistance that varies according to storage data magnetically written therein. The plurality of write digit lines are arranged respectively corresponding to the plurality of memory cell rows, for passing therethrough a prescribed current of a fixed direction in a selected row in data write operation. The plurality of bit lines are arranged respectively corresponding to the plurality of memory cell columns for passing therethrough a data write current of a direction corresponding to a level of write data in a selected column in the data write operation. The first and second write current control lines are respectively provided at both ends of the plurality of bit lines so as to extend in a direction along the memory cell rows, and shared by the plurality of bit lines. The first connection control portion connects one of the first and second write current control lines to a first voltage in the data write operation. The second connection control portion connects the other write current control line to a second voltage in the data write operation. The plurality of column selection lines are arranged respectively corresponding to the plurality of memory cell columns, and activated in a selected column. The write drivers are provided respectively corresponding to the memory cell columns. Each write driver connects a corresponding one of the bit lines between the first and second write current control lines in response to activation of a corresponding one of the plurality of column selection lines.
In the above thin film magnetic memory device, a data write current is supplied to the selected bit lines through the write current control lines shared by the plurality of memory cell columns. As a result, the structure of the write drivers provided corresponding to the respective bit lines can be simplified, enabling reduction in area of the MRAM device.
According to a further aspect of the present invention, a thin film magnetic memory device includes a memory array, a plurality of write digit lines, a plurality of bit lines, a plurality of column selection lines, and a plurality of write drivers. The memory array has a plurality of memory cells arranged in a matrix. Each memory cell has an electric resistance that varies according to storage data magnetically written therein. The memory array is divided into a plurality of memory blocks along a direction of the memory cell rows. The plurality of write digit lines are arranged respectively corresponding to the plurality of memory cell rows, for passing therethrough a prescribed write current of a fixed direction in a selected row in data write operation. The plurality of bit lines are arranged respectively corresponding to the plurality of memory cell columns. In each memory cell column, the bit line is divided by the plurality of memory blocks. The plurality of column selection lines are arranged respectively corresponding to the plurality of memory cell columns, for transmitting a column selection result. Each column selection line is shared by the plurality of memory blocks. The plurality of write drivers are provided respectively corresponding to the plurality of bit lines. Each write driver operates in response to activation of a corresponding one of the plurality of column selection lines to supply a data write current of a direction corresponding to a level of write data to a corresponding one of the plurality of bit lines.
In the above thin film magnetic memory device, the memory array is divided into a plurality of memory blocks in the row direction, and the column selection result can be transmitted to each memory block without increasing the number of signal lines. This enables the capacity of the memory array to be increased efficiently.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.